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1 ? caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved all other trademarks mentioned are the property of their respective owners. 8-bit, 40/60/75/80 ms ps a/d converter the HI5714 is a high precision, monolithic, 8-bit, analog-to- digital converter fabricated in intersil? advanced hbc10 bicmos process. the HI5714 is optimized for a wide range of applications such as ultrasound imaging, mass storage, instrumentation, and video digitizing, where accuracy and low power consumption are essential. the HI5714 is offered in 40 msps, 60 msps, and 75 msps sample rates. the HI5714 delivers 0.4 lsb differential nonlinearity while consuming only 325mw power (typical) at 75 msps. the digital inputs and outputs are ttl compatible, as well as allowing for a low-level sine wave clock input. features ? sampling rate . . . . . . . . . . . . . . . . . . . 40/60/75/80 msps ? low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325mw ? 7.65 enob at 4.43mhz ? overflow/underflow three-state ttl output ? operates with low level ac clock ? very low analog input capacitance ? no buffer amplifier required ? no sample and hold required ? ttl compatible i/o ? pin-compatible to philips tda8714 applications ? video digitizing ? qam demodulator ? digital cable setup box ? tape drive/mass storage ? medical ultrasound imaging ? communication systems pinoutpinout HI5714 (soic) top view ordering information part number temp. range ( o c) package sampling frequency (mhz) pkg. no. HI5714/4cb 0 to 70 24 ld soic 40 m24.3 HI5714/7cb-t 0 to 70 24 ld soic tape & reel 75 m24.3 HI5714eval 25 evaluation board 1 2 3 4 5 6 7 8 9 10 11 12 d1 d0 nc v rb nc agnd v cca v in v rt nc o/uf d7 16 17 18 19 20 21 22 23 24 15 14 13 d2 oe v cco2 ognd v cco1 dgnd d4 d5 d6 d3 v ccd clk fn3973.5 HI5714 data sheet april 2003
2 functional block diagram typical application schematic notes: 1. pin 5 should be connected to agnd and pins 3 and 10 to dgnd to reduc e noise coupling into the device. 2. analog and digital supplies should be separated and decoupled to reduce digital noise coupli ng into the analog supply. analog to digital converter latches ttl outputs ttl output overflow/underflow latch clock driver v cca clk v ccd oe v rt v rb ognd agnd dgnd v cco1 v cco2 o/uf v in 1 2 4 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 d7 d6 d5 d4 d3 d2 d1 d0 12 13 14 15 23 24 1 2 v rb HI5714 v rt clk dgnd nc nc agnd v cca v ccd d7 d6 d5 d4 d3 d2 d1 d0 as close to part as possible. 1nf and 0.1 f caps are placed clock v in nc v in ognd v cco v cco +5va o/uf bnc dgnd agnd oe 11 19 21 18 20 3 17 10 16 9 4 8 7 5 6 22 3.6v 1.3v +5va +5vd 1nf 0.1 f 1nf 0.1 f 0.1 0.1 - + - + - + HI5714
3 absolute m aximum ratings t a = 25 o c thermal information v cca , v ccd , v cco . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.0v v cca - v ccd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3v v cco - v ccd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3v v cca - v cco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3v v in , v clk , v rt , v rb , oe . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.0v i out , digital pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma input current, all pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1ma digital i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ognd to v cco operating conditions temperature range HI5714/xcb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 1) ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 maximum junction temperature (plastic package) . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications v cca = v ccd = v cco = +5v; v rb = 1.3v; v rt = 3.6v; t a = 25 o c, unless otherwise specified parameter test condition min typ max units clock (referenced to dgnd) (note 2) logic input voltage low, v il 0 - 0.8 v logic input voltage high, v ih 2.0 - v ccd v logic input current low, i il v clk = 0.4v -400 - - a logic input current high, i ih v clk = 2.7v - - 300 a input impedance, z in f clk = 75mhz (note 9) - 2 - k ? input capacitance, c in f clk = 75mhz (note 9) - 4.5 - pf oe (referenced to dgnd) logic input voltage low, v il 0 - 0.8 v logic input voltage high, v ih 2.0 - v ccd v logic input current low, i il v il = 0.4v -400 - - a logic input current high, i ih v ih = 2.7v - - 20 a v in (referenced to agnd) input current low, i il v in = 1.2v - 0 - a input current high, i ih v in = 3.5v - 100 180 a input impedance, z in f in = 4.43mhz - 10 - k ? input capacitance, c in f in = 4.43mhz - 14 - pf reference input bottom reference range, v rb 1.2 1.3 1.6 v top reference range, v rt 3.5 3.6 3.9 v reference range, v ref (v rt - v rb ) 1.9 2.3 2.7 v reference current, i ref - 10 - ma reference ladder resistance, r lad - 240 - ? r ladtc - 0.24 - ? / o c bottom offset voltage, v ob (note 5) - 255 - mv v obtc (note 5) - 136 - v/ o c top offset voltage, v ot (note 5) - -300 - mv v ottc (note 5) - 480 - v/ o c HI5714
4 digital outputs (d0 to d7 and o/uf referenced to ognd) logic output voltage low, v ol i o = 1ma 0 - 0.4 v logic output voltage high, v oh i o = -0.4ma 2.7 - v cco v output leakage current, i d 0.4v < v out < v cco -20 - +20 a switching characteristics (notes 4, 5) see figure 1 sample rate, f clk HI5714/7 75 - - mhz HI5714/4 40 - - mhz clock pulse width high, t cph 6 - - ns clock pulse width low, t cpl 6 - - ns analog signal processing (f clk = 40mhz) differential gain, dg (notes 6, 9) - 1.0 - % differential phase, dp (notes 6, 9) - 0.05 - degree harmonics (f clk = 75mhz) second harmonic, h2 f in = 4.43mhz - -63 - db third harmonic, h3 f in = 4.43mhz - -65 - db total harmonic distortion, thd f in = 4.43mhz - -59 - db spurious free dynamic range, sfdr f in = 4.43mhz - 62 - db analog input bandwidth (-3db) - 18 - mhz transfer function differential linearity error, dnl (note 7) - 0.4 - lsb integral linearity error, inl (note 7) - 0.75 - lsb effective number of bits enob HI5714/4 (f clk = 40mhz) f in = 4.43mhz - 7.65 - bits f in = 7.5mhz - 7.5 - bits HI5714/7 (f clk = 75mhz) f in = 4.43mhz - 7.4 - bits f in = 7.5mhz - 7.15 - bits f in = 10mhz - 6.8 - bits bit error rate, ber (note 8) - 10 -11 - times/ sample timing (f clk = 75mhz) see figures 1, 2 sampling delay, t sd - - 2 ns output hold time, t hd 5 - - ns output delay time, t d HI5714/4/7 - 10 13 ns output enable delay, t pzh enable to high - 14.6 - ns output enable delay, t pzl enable to low - 17.8 - ns output disable delay, t phz disable from high - 5.3 - ns output disable delay, t plz disable from low - 6.7 - ns aperture jitter, t aj - 50 - ps electrical specifications v cca = v ccd = v cco = +5v; v rb = 1.3v; v rt = 3.6v; t a = 25 o c, unless otherwise specified (continued) parameter test condition min typ max units HI5714
5 power supply characteristics analog power supply range, v cca 4.75 5.0 5.25 v digital power supply range, v ccd 4.75 5.0 5.25 v output power supply range, v cco 4.75 5.0 5.25 v total supply current - 65 75 ma supply current, i cca - 30 - ma supply current, i ccd - 26 - ma supply current, i cco - 9 - ma power dissipation - 325 375 mw notes: 2. dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 3. the supply voltages v cca and v ccd may have any value between -0.3v and +6v as long as the difference v cca - v ccd lies between -0.3v and +0.3v. 4. in addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock not be less than 1ns. 5. analog input voltages producing code 00 up to and including ff. v ob (bottom offset voltage) is the difference between the analog input which produces data equal to 00 and the bottom reference voltage (v rb ). v obtc (bottom offset voltage temperatur e coefficient) is the variation of v ob with temperature. v ot (top offset voltage) is the difference between the top reference voltage (v rt ) and the analog input which produces data output equal to ff. v ottc (top offset voltage temperature c oefficient) is the variation of v ot with temperature. 6. input is standard 5 step video test signal. a 12-bit r reconstruct dac and vm700 are used for measurement. 7. full scale sinewave, f in = 4.43mhz. 8. f clk = 75mhz, f in = 4.43mhz, v in = 8 lsb at code 128, 50% clock duty cycle. 9. parameter is guaranteed by design, not production tested. electrical specifications v cca = v ccd = v cco = +5v; v rb = 1.3v; v rt = 3.6v; t a = 25 o c, unless otherwise specified (continued) parameter test condition min typ max units HI5714
6 timing waveforms figure 1. input-to-output timing figure 2. three-state timing circuit analog input clock input data (d0-d7) outputs t d t ds t hd 2.4v 1.4v 0.4v 1.4v t cpl t cph sample n sample n + 1 sample n + 2 d n - 2 d n - 1 d n + 1 d n oe digital output digital output t pzl t pzh t plz t phz 1.4v 1.4v 0v 0v v oh v ol 0.3v 0.3v 3.5v input 4v HI5714
7 typical performance curves figure 3. total i cc vs temperature figure 4. integral linearity error vs temperature figure 5. differential linearity error vs temperature figure 6. reference resistance vs temperature figure 7. v ot vs temperature figure 8. v ob vs temperature 70 60 50 40 30 20 10 0 -40-30-20-10 0 1020304050607080 temperature ( o c) ma 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 -40-30-20-10 0 1020304050607080 temperature ( o c) lsb 90 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 -40-30-20-100 1020304050607080 temperature ( o c) lsb -0.2 -0.1 0 90 270 260 250 240 230 220 210 200 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ( o c) ohms 280 -230 -240 -250 -260 -270 -280 -290 -320 -40-30-20-100 1020304050607080 temperature ( o c) mv -220 -300 -310 250 240 230 210 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ( o c) mv 260 220 HI5714
8 pin descriptions pin number symbol description 1, 2, 12-15, 23, 24 d0 to d7 digital outputs, d0 (lsb) to d7 (msb). 4 v rb bottom reference voltage input. range: 1.2v to 1.6v. 6 agnd analog ground. 7 v cca analog +5v. 8 v in analog input. 9 v rt top reference voltage input. range: 3.5v to 3.9v. 11 o/uf underflow/overflow digital output. goes high if the analog input goes above or below the reference (v rb , v rt ) minus the offset. 16 clk clock input. 17 dgnd digital gnd. 18 v ccd digital +5v. 19, 21 v cco1 , v cco2 digital +5v for digital output stage. 20 ognd digital ground for digital output stage. 22 oe output enable high: digital outputs are three-stated. low: digital outputs are active. table 1. a/d code table code description (note 1) input voltage v rt = 3.6v v rb = 1.3v o/uf binary output code d7 d6 d5 d4 d3 d2 d1 d0 underflow <1.555v 1 0 0 0 0 0 0 0 0 0 1.555v 0 0 0 0 0 0 0 0 0 1 - 0 - - - - - - - - - - 0 - - - - - - - - - - 0 - - - - - - - - 254 - 0 1 1 1 1 1 1 1 0 255 3.300v 0 1 1 1 1 1 1 1 1 overflow >3.300v 1 1 1 1 1 1 1 1 1 note: 10. the voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage, incl uding the typical reference offset voltages. table 2. mode selection oe d7 to d0 o/uf 1 high impedance high impedance 0 active: binary active HI5714
9 detailed description theory of operation the HI5714 design utilizes a folding and interpolating architecture. this architecture reduces the number of comparators, reference taps, and latches, thereby reducing power requirements, die size and cost. a folding a/d converter operates basically like a 2 step subranging converter by using 2 lower resolution converters to do a course and subranged fine conversion. a more complete description is given in the application note ?using the HI5714 evaluation module? (an9517). reference input, v rt and v rb the HI5714 requires an external reference to be connected to pins 4 and 9, v rb and v rt . it is recommended that adequate high frequency decoupling be provided at the reference input pin in order to minimize overall converter noise. a 0.1 f and a 1nf capacitor as close as possible to the reference pins work well. v rt must be kept within the range of 3.5v to 3.9v and v rb within 1.2v to 1.6v. if the re ference voltages go outside their respective ranges, the input folding amplifiers may saturate giving erroneous digital data. the range for (v rt - v rb ) is 1.9v to 2.7v, which defines the analog input range. digital control and clock requirements the HI5714 provides a standard high-speed interface to external ttl logic families. the outputs can be thr ee-stated by setting the oe input (pin 22) high. the clock input operates at standard ttl levels as well as a low level sine wave around the threshold level. the HI5714 can operate with clock frequencies from dc to 75mhz. the clock duty cycle should be 50% 10% to ensure rated performance. duty cycle vari ation, within the specified range, has little effect on performance. due to the clock speed it is important to remember that clock jitter will affect the quality of the digital output data. the clock can be stopped at any time and restarted at a later time. once restarted the digital data will be valid at the second rising edge of the clock plus the data delay time. digital outputs and o/uf output the digital outputs are st andard ttl type outputs. the HI5714 can drive 1 to 3 ttl inputs depending on the input current requirements. should the analog input exceed the top or bottom reference the over/underflow output (pin 11) will go high. should the analog input exceed the t op reference voltage, v rt , the digital outputs will remain at all 1s until the analog input goes below v rt . also, should the analog input go below the bottom reference voltage, v rb , the digital outputs will remain at all 0s until the analog input goes above v rt . analog input the analog input will accept a voltage within the reference voltage levels, v rb and v rt , minus some offset. the offset is specified in the electr ical specifications table. the analog input is relatively high impedance (10k ? ) but should be driven from a low impedance source. the input capacitance is low (14pf) and there is little kickback from the input, so a series resistance is not necessary but it may help to prevent the driving amplifier from oscillating. the input bandwidth is typically 18mhz. exceeding 18mhz will result in sparkle at the digital outputs. the bandwidth remains constant at cl ock rates up to 75mhz. supply and ground considerations in order to keep digital noise out of the analog signal path, the HI5714 has separate analog and digital supply and ground pins. the part should be mounted on a board that provides separate low impeda nce connections for the analog and digital supplies and grounds. the analog and digital grounds should be tied together at one point near the HI5714. t he grounds can be connected directly, through an inductor (ferrite bead), or a low valued resistor. dgnd and agnd can be tied together. to help minimize noise, tie pin 5 (nc) to agnd and pins 3 (nc) and 10 (nc) to dgnd. for best performance, the supplies to the HI5714 should be driven by clean, linear regulated supplies. the board should also have good high frequency leaded decoupling capacitors mounted as close as possible to the converter. capacitor leads must be kept as short as possible (less than 1 / 2 inch total length). a 0.1 f and a 1nf capacitor as close as possible to the pin works well. chip capacitors will provide better high frequency decoupling but leaded capacitors appear to be adequate. if the part is to be powered by a single supply, then the analog supply pins should be isolated by ferrite beads from the digital supply pins. this should help minimize noise on the analog power pins. refer to application note an9214, ?using intersil high speed a/d converters?, for additional considerations when using high speed converters. increased accuracy further calibration of the adc can be done to increase absolute level accuracy. first, a precision voltage equal to the ideal vin -fs + 0.5 lsb is applied at v in . adjust v rb until the 0 to 1 transition occurs on the digital output. next, a voltage equal to the ideal vin +fs - 1.5 lsb is applied at v in . v rt is then adjusted until the 254 to 255 transition occurs on the digital output. HI5714
10 applications figures 9 and 10 show two possible circuit configurations, ac coupled with a dc restore circuit and dc coupled with a dc offset amplifier. due to the high clock rate, fc t (ttl/cmos) or fast (ttl) glue logic should be used. fct logic will tend to have large overshoots if not loaded. long tr aces (>2 or 3 inches) should be terminated to maintain signal integrity. figure 9. typical ac coupled input with dc restore figure 10. typical dc coupled input 12 13 14 15 23 24 1 2 v rb HI5714 v rt clk dgnd nc nc agnd v cca v ccd d7 d6 d5 d4 d3 d2 d1 d0 clock v in nc v in ognd v cco v cco +5va o/uf oe 11 19 21 18 20 3 17 10 16 9 4 8 7 5 6 22 3.6v 1.3v +5va +5vd 10 0.1 10 0.1 0.1 0.1 sample pulse dc restore - + - + 12 13 14 15 23 24 1 2 v rb HI5714 v rt clk dgnd nc nc agnd v cca v ccd d7 d6 d5 d4 d3 d2 d1 d0 clock v in nc v in ognd v cco v cco +5va o/uf oe 11 19 21 18 20 3 17 10 16 9 4 8 7 5 6 22 3.6v 1.3v +5va +5vd 10 0.1 10 0.1 0.1 0.1 +5va offset - + - + - + HI5714
11 timing definitions aperture delay: aperture delay is the time delay between the external sample command (the rising edge of the clock) and the time at which the signal is actually sampled. this delay is due to internal clock path propagation delays. aperture jitter: this is the rms variation in the aperture delay due to variation of internal clock path delays. data latency after the analog sample is taken, the data on the bus is output at the next rising edge of the clock. this is due to the output latch of the converter. th is delay is specified as the data latency. after the data latency time, the data representing each succeeding sample is output at the following clock pulse. the digital data lags the analog input by 1 cycle. static performance definitions offset error and full-scale error use a measured value of the external voltage reference to determine the ideal plus and minus full-scale values. the results are all displayed in lsbs. bottom offset voltage (v ob ) the first code transition should occur at a level 0.5 lsb above the negative full-scale. bottom offset voltage is defined as the deviation of the actual code transition from this point. top offset voltage (v ot ) the last code transition should occur for a analog input that is 1.5 lsbs below positive fu ll-scale. top offset voltage is defined as the deviation of the actual code transition from this point. differential linearity error (dnl) dnl is the worst case deviatio n of a code width from the ideal value of 1 lsb. the converter is guaranteed to have no missing codes. integral linearity error (inl) inl is the worst case deviation of a code center from a best fit straight line calculated from the measured data. figure 11. 8-bit video components a/d d/a dsp/ p reference icl8069 amp amp ha5020 (single) ha5022 (dual) ha5024 (quad) ha5013 (triple) hfa1105 (single) hfa1205 (dual) hfa1405 (quad) HI5714 (8-bit) hsp9501 hsp48410 hsp48908 hsp48901 hsp48212 hsp43881 hsp43168 hi1171 (8-bit) ca3338 (8-bit) hi5721 (10-bit) ha5020 (single) ha2842 (single) hfa1115 (single) hfa1212 (dual) hfa1412 (quad) cmos logic available in fct hsp9501: programmable data buffer hsp48410: histogrammer/accumulating buffer, 10- bit pixel resolution, 4k x 4k frame size hsp48908: 2-d convolver, 3 x 3 kernal convolution, 8-bit hsp48901: 3 x 3 image filter, 30mhz, 8-bit hsp48212: video mixer hsp43881: digital filter, 30mhz, 1-d and 2-d fir filters hsp43168: dual fir filter, 10-bit, 33/45mhz hi3050 (10-bit) HI5714
12 dynamic performance definitions fast fourier transform (fft) techniques are used to evaluate the dynamic perform ance of the HI5714. a low distortion sine wave is applied to the input, it is sampled, and the output is stored in ram. the data is then transformed into the frequency domain with a 2048 point fft and analyzed to evaluate the dynamic performance of the a/d. the sine wave input to the part is 0.5db down from full scale for these tests. the distorti on numbers are quoted in dbc (decibels with respect to carrier) and do not include any correction factors for normalizing to full scale. signal-to-noise ratio (snr) snr is the measured rms signal to rms noise at a specified input and sampling frequency. the noise is the rms sum of all of the spectral components except the fundamental and the first five harmonics. signal-to-noise + distortion ratio (sinad) sinad is the measured rms si gnal to rms sum of all other spectral components below the nyquist frequency excluding dc. effective number of bits (enob) the effective number of bits (enob) is derived from the sinad data. enob is calculated from: enob = (sinad - 1.76) / 6.02 2nd and 3rd harmonic distortion this is the ratio of the rms value of the 2nd and 3rd harmonic component respective ly to the rms value of the measured input signal. full power input bandwidth full power bandwidth is the frequency at which the amplitude of the digitall y reconstructed output has decreased 3db below the amplit ude of the input sine wave. the input sine wave has a peak-to-peak amplitude equal to the difference between the top reference voltage input and the bottom reference voltage input. the bandwidth given is measured at the specified sampling frequency. HI5714
13 die characteristics die dimensions: 134 mils x 134 mils x 19 mils 1 mil metallization: type: alsicu thickness: m1 - 8k ? , m2 - 17k ? substrate potential (powered up): gnd (0.0v) passivation: type: sandwich passivation* undoped silicon glass (usg) + nitride thickness: usg - 8k ? , nitride - 4.2k ? total 12.2k ? + 2k ? worst case current density: 1.6 x 10 4 a/cm 2 transistor count: 3714 die attach: silver filled epoxy metallization mask layout HI5714 do d1 d2 d3 oe o/uf d7 d6 d5 d4 v rb agnd v cca v rt v in v cc02 ognd v cc01 dgnd v ccd clk HI5714
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com HI5714 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millime ter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m24.3 (jedec ms-013-ad issue c) 24 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.020 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.5985 0.6141 15.20 15.60 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n24 247 0 o 8 o 0 o 8 o - rev. 0 12/93

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